The invention relates to an IC testing apparatus and a testing method using the apparatus which are used to execute a DC test in which a direct current or d. c. voltage is applied to a terminal on an IC under test to examine a voltage or current characteristic occurring at that terminal and a functional test to see whether or not the IC operates normally.
FIG. 1 is an illustration of a conventional IC testing apparatus in summary. IC testing apparatus 20 comprises a DC tester 30, a functional tester 40 and a controller 50 which controls both of them.
A DC test includes a current-applied voltage measuring test in which a known current is passed through a terminal P of an IC under test 10 to determine a voltage VX developed at the terminal P to see if the voltage VX lies within a predetermined voltage range, and a voltage-applied current measuring test to examine if a predetermined current passes through the terminal P of the IC under test when a given voltage is applied to the terminal.
The DC tester 30 shown in FIG. I indicates an arrangement for the current-applied voltage measuring test. Specifically, in this test, the tester 30 includes a current source 31 and voltage measuring means 32. The current source 31 supplies a current IS of a known magnitude to the terminal P of the IC under test 10 through a force line FOR. The voltage measuring means 32 then determines a voltage VX which is developed at the terminal P of the IC under test 10 through a sense line SEN.
FIGS. 2 and 3 graphically show maximum assurance characteristic curves CL1 and CL2 and minimum assurance characteristic curves CL and CL4 based on results of measurement of current-voltage responses of P-channel FET 61 and N-channel FET 62 contained in output means 60 of the IC under test 10. In the current-applied voltage measuring test, a predetermined current IOH or IOL is passed through the terminal P to measure a resulting voltage VDS developed at the terminal P in order to determine if the resulting voltage-current response is contained in a range defined between the maximum and the minimum assurance characteristic curve, thus determining if the IC under test 10 is acceptable or faulty.
A first switch S1 and a second switch S2 are connected in series with the sense line SEN and the force line FOR, respectively. The first switch S1 and the second switch S2 are controlled by the controller 50 to be turned on for the direct current test and turned off for the functional test. In FIG. 1, a resistor R1 shown within a block indicated by S1 represents an on resistance of the switch S1 when it is turned on. Similarly, a resistor R2 shown within a block indicated by S2 represents an on resistance of the switch S2.
The functional tester 40 comprises a driver DR which applies a test pattern signal to the IC under test 10, a voltage comparator CP which determines whether or not a response signal from the IC under test 10 has a logic level of a voltage which satisfies a voltage requirement, and a programmable load PL which is used to examine ira given current IH or IL passes through the terminal P of the IC under test 10 during the functional test, with a common junction between the driver DR, the voltage comparator CP and the programmable load PL being connected to the terminal P of the IC under test 10 through a third switch S3. While not shown, it should be understood that the functional tester 40 also includes a function of generating a test pattern to be applied to the driver DR, a function of confirming that a proper logic level is delivered from the output of the voltage comparator CP at a preset timing or like functions, in a similar manner as in known IC testing apparatus. During the functional test, in order to determine if a voltage delivered from the terminal P of the IC under test 10 has a proper logic level, it is necessary that the driver DR exhibits a sufficiently high output impedance so as to be substantially isolated from the voltage comparator CP while a reference voltage VOH of a high logic level (H) be applied to the inverting input terminal of a voltage comparator CP1 and a reference voltage VOL of a low logic level (L) be applied to the non-inverting input terminal of a voltage comparator CP2. An output voltage from the terminal P of the IC under test 10 is compared against the reference voltages VOH and VOL by the voltage comparators CP1 and CP2, respectively. If the output voltage of the IC under test 10 assumes a proper high logic level, the voltage comparator CP1 delivers a high level output. If the output voltage of the IC under test 10 assumes a proper low logic level, the voltage comparator CP2 delivers a high level output. The controller 50 arranges for a sufficiently high output impedance of the driver DR and sets up the reference voltages VOH and VOL. During the functional test, the controller 50 also turns the third switch S3 on and turns the first switch S1 and the second switch S2 off.
FIG. 4 shows an arrangement of the DC tester 30 for the voltage-applied current measuring test. In this instance, the current source 31 is formed by an operational amplifier OP having its non-inverting input terminal connected to a voltage source 33 to receive a voltage EV therefrom. The operational amplifier OP also includes an output terminal which is connected through a force line FOR to a terminal P of an IC under test 10. A current detecting resistor Ri and a second switch S2 are connected in series in the force line FOR to apply a voltage to the terminal P of the IC under test 10. A voltage at the terminal P is fed back to the inverting input terminal of the operational amplifier OP through a sense line SEN and a first switch S1. The feedback is effective to maintain a voltage EV' which is applied to the terminal P of the IC under test 10 to be equal to the voltage EV of the voltage source 33. The arrangement allows any voltage of a known value to be applied to the terminal P of the IC under test 10 by choosing an arbitrary value for the voltage EV of the voltage source 33. Under the condition that a known voltage is applied, a voltage developed across the current detecting resistor Ri is measured by voltage measuring means 34, thus determining a current IOL or IOH which is either supplied to the IC under test 10 through the force line FOR or discharged from the IC under test 10 through the force line FOR. In this manner, the combination of the current detecting resistor Ri and the voltage measuring means 34 defines current measuring means IM.
The first switch S1 and the second switch S2 are turned on, during the voltage-applied current measuring test, but are turned off during the functional test to isolate the direct current tester 30 from the terminal P of the IC under test 10. During the DC test, the third switch S3 is controlled to be turned off, thus isolating the functional tester 40 from the terminal P of the IC under test 10, in the similar manner as shown in the arrangement of FIG. 1. Such controls are exercised by the controller 50.
As mentioned, the third switch S3 is provided to isolate the functional tester 40 during the DC test, while the first switch S1 and the second switch S2 are provided to isolate the DC tester 30 during the functional test. In the conventional practice, these switches S1 to S3 are served by reed relays. Reed relays are used for the reason that when used as the first to the third switch S1, S2 and S3, they exhibit a low on resistance, as represented by R1, R2 and R3, and allow for a relatively high current capacity on the order of 0.3 to 0.5 A, permitting a single reed relay to feed an amount of current which may be passed to the IC under test 10.
Specifically, the DC test includes a mode in which a direct current response of an IC under test is examined with a current flow in a normal range which may be on the order of 4 to 50 mA, and an overload test which examines whether or not a given current flow occurs in the event of a short-circuit condition. The overload current which may occur during the overload test is on the order of 50 mA to 200 mA at most, which can be satisfactorily served by a single reed relay.
However, because the reed relay comprises a mechanical contact structure, it suffers from a limited useful life, presenting problems in respect of reliability and durability.
To cope with these problems, it may be contemplated to use semiconductor switches for the first to the third switch S1, S2 and S3, as shown in FIG. 5. To be used as such a semiconductor switch, a semiconductor switching element of a type which can be turned on or off in response to light emission from a light emitting element would be generally useable. The reliability and the durability could be improved by the use of such a semiconductor switch, which however causes difficulties as mentioned below.
Specifically, semiconductor switches S1, S2 and S3 would exhibit relatively large on resistances R1, R2 and R3 and also relatively large off capacitances, which are notable drawbacks. The term an off capacitance is understood as a capacitance between contacts of a mechanical switch when it is off. Considering the DC test, the presence of a relatively large on resistance causes an inconvenience that a high current flow is precluded.
Turning to the functional test, the on resistance R3 of the third switch S3 will be connected in series with a signal transmission line LIN on the output side of the driver DR, and there will be created a current flow through the signal transmission line LIN which has the DC tester 30 connected as a load, the flow passing to a point of a common potential through a parallel connection of off capacitances C1 and C2 of the first switch S1 and the second switch S2, as shown in FIG. 6. If the DC tester 30 exhibits a low impedance, an increase in the capacitance of the off capacitors C1 and C2 causes an increased current flow to the DC tester 30, which in turn causes a significant degradation in the waveform quality of a test pattern signal that is transmitted on the signal transmission line LIN.
To conduct an overload test, it is demanded that the second switch S2 has a high current capacity. It is then desirable to use a semiconductor switch having a reduced on resistance for the second switch S2. A semiconductor switch having a reduced on resistance R2 would be manufactured by increasing the cross-sectional area of a portion of the semiconductor switch through which the current passes. This increases the off capacitance C2 disadvantageously. Conversely, if a semiconductor switch with a reduced off capacitance C2 is manufactured, the resulting on resistance would increase, thus presenting conflicting requirements. While it may be contemplated to construct a semiconductor switch with a reduced on resistance by a parallel connection of semiconductor switches each having a reduced off capacitance, an outcome of this is the fact that the parallel connection of a plurality of off capacitances results in an even greater off capacitance. A recent trend is toward an even higher operational speed of the functional test, and a demand then is a minimized off capacitance, which may be equal to or less than 1 pF, for the switches S1 and S2. The manufacture of a semiconductor switch with an off capacitance equal to or less than 1 pF may not be impossible, but results in a semiconductor switch having an increased on resistance, which disadvantageously involves an insufficient current capacity to be used as the second switch S2 which is required to pass an increased current flow.
For these reasons, where semiconductor switches are used as the switches S1 and S2, there results a disadvantage that an overload test can not be conducted.
It is an object of the invention to provide an IC testing apparatus connected to an output of a DC tester and incorporating semiconductor switches as a first switch S1 and a second switch S2 which may connect the DC tester to a terminal of an IC under test or to interrupt such connection while enabling an overload test during a DC test.